Ranjana Narang

About Ranjana Narang

I have 20+ years experience in the field of ASIC design and verification mainly in data networking. Involved in all phases of the development from micro-architecture, design, verification, bring up, vector generation to wafer debug. I enjoy being very hands one and I am always on the look out to improve the verification environment. I also enjoy integrating the latest methodologies in the verification environment at the same time I am very technical and enjoy driving the project from start to finish.My skill set is as follows.• Hardware Description Languages: VHDL, System Verilog.• Simulation Tools: VCS & MixedHDL from Synopsys, and ModelTech, Verilog XL, Verdi• Synthesis Tools: Design Compiler from Synopsys & Leonardo Synthesis Tool from Exemplar.• Code Coverage Tool: CoverMeter from Synopsys, Vcover.• Verification tool- VERA, RVM, SV, OVM, UVM, Specman.• Lint tool – Spyglass.• CDC – 0in.• Formal Verification – LEC, Virplex from Cadence.• Programming Languages: C, Assembly – 68040, 68302 & 8085,PALASM, Abel.• Board Level Design Tools: Orcad, Dazix, Ace & Aceplus. Boardmaster.• Programmable Logic Design tools: Complete toolset for FPGA’s, EPLD’s & PAL’s. • Debugging Tools : Undertow, Internal Logical Analyzer (ILA).PCIe Analyzer• Translation Tools : Interhdl’s V2VL (VHDL to verilog).

Experience

1. Principal Validation Engineer, Validation Lead

   NVIDIA

   Aug 2021 — Present · Santa Clara County, CA, US

Education

• Shivaji University

  B.E, Electronics and telecommunications

Skills

• Computer Architecture
• Debugging
• Soc
• Functional Verification
• Rtl Design
• Integrated Circuit Design
• Microprocessors
• Verilog
• Vlsi
• Systemverilog
• Vhdl
• Static Timing Analysis
• Fpga
• Asic
• Ic