Rani Paga
A&MS Senior Layout Engineer at Synopsys | 3.5+ Experince | Specialized in 55nm/8nm/4nm/3nm/2nm | Worked nodes Intel · TSMC · Samsung · Rapidus · Global Foundary | Advanced Nodes
- Role
- Senior Engineer at Eximietas Design
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Rani Paga
3.5+ years experience in across advanced nodes including 4/3/2, 18, 8/4/2 & 2, 55(12)Hands-on experience in, including op-amp layout techniques in 3nm technode.Worked on 6 in 3nm technode with an understanding of Expertise in special cells, Combinational, sequential like multi-bit cells, level shifters, retention cells, and via ladder development and key contributor to Hybrid N3 Library (M143/M195)Tool based in Layout utilities for improving workflow efficiencyDelivered 100% DRC/LVS-clean, DFM-compliant layouts with strong focus on PPA optimization & pin-access improvementAnalog layout techniques,/ Hands-on experience with, 2, and advanced verification methodologies#Good understanding of submicron and #Knowledge on digital and analog layout techniques#Worked on IC verification#Expertise in /,## Basics
Experience
Senior Engineer
Feb 2026 — Present
SerDes Custom Layout ODC projectsDesigning floor planning of Digital blocks
Education
Sri Chaithanya Jr. College
Intermediate, MPC
2012 — 2014
Don Bosco High School - India
SSC
National Institute of Technology, Tiruchirappalli
Master of Technology - MTech
National Institute of Technology Surat
Bachelor of Technology, Electronics and Communication Engineering
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