Rangala Sandeep Kumar

About Rangala Sandeep Kumar

As a Design Engineer II at Cadence Design Systems, I apply my expertise in Spyglass, a leading tool for static and formal verification of ASIC and FPGA designs. I have an MTech degree in VLSI Design Automation & Techniques from NIT Hamirpur and a BTech degree in Electronics and Communications Engineering from Sri Krishnadevaraya University.I contribute to the design and verification of complex SoCs, using Verilog, Xilinx Vivado, and Synopsys Formality. I handle Spyglass Lint and CDC cleanup, checking and resolving issues such as metastability, data loss, and data incoherency. I also trace and solve various errors with the help of CDC rules and incremental schematic. Previously, I designed an APB to SPI bridge and a low power voltage reference circuit for medical devices at TECHNOLOGIES PRIVATE LIMITED. I am self-motivated, hard-working, and ambitious, with a positive attitude to learning new things.

Experience

1. Design Engineer Ii

   Cadence

   Sep 2023 — Present · Bengaluru, IN

Education

• Sri Krishnadevaraya University

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2012 — 2016

• National Institute of Technology Hamirpur-Alumni

  Master of Technology - MTech, VLSI Design Automation & Techniques (VDAT)

  2017 — 2019