Randy Butera
Retired Senior Technical Lead and Electrical Validation Architect at Intel
- Role
- Senior Technical Lead and Electrical Validation Architect at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Randy Butera
Objective: I want to challenge myself and learn. New horizons and all…
Experience
Senior Technical Lead and Electrical Validation Architect
Jan 1999 — Present
Education
California Polytechnic State University-San Luis Obispo
Mechanical Engineering
1978 — 1980
California Polytechnic State University-San Luis Obispo
Aerospace, Aeronautical and Astronautical Engineering
1974 — 1978
Skills
- Analog Circuit Design
- Testing Instruments
- System on a Chip (Soc)
- Soc
- Power Management
- Usb
- Sensors
- Robotics
- Dp
- Testing
- Electrical Engineering
- Server Architecture
- Fpga
- Signal Integrity
- Pll
- Computer Architecture
- Metrology
- Embedded Systems
- Hdmi
- Mipi
- Semiconductors
- Integrated Circuit Design
- Microprocessors
- Intel
- Mixed Signal
- Circuit Design
- Firmware
- Product Design
- Computer Hardware
- Pcie
- Compliance
- Dft
- Debugging
- Project Management
- Silicon
- Pcb Design
- Python
- Validation
- Physical Design
- Processors
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.