Randolph Cruz
Senior Principal Engineer of Ic Package R & d @Intersil Acquired By Renesas
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WORK HISTORY
Senior Principal Engineer of Ic Package R & d @Intersil Acquired By Renesas
Palm Bay, FL, US
Senior Principal EngineerPrincipal Engineer, - 2012 Guided Package Technology R&D for Power Management IC product development including cost analysis from concept to production ramp: package architecture definition, design & development with assembly sub-contractors and partners, prototyping, qualification and pre-production builds. Championed migration from conventional leaded packages (e.g. SOP/PDIP/QFP) to reduced outline and advance packaging with body sizes from <2mmx2mm to 17mmx19mm (e.g. QFN, DFN, HDA, Ultra-Thin Q/DFN Chip-On-Lead, Stacked-Die, WLCSP, Cu Clip Interconnect and MCM/SiP/Modules). Provided Technology Development and NPI support for design centers in FL, CA, UK, NC, NJ, and TX. Kept packaging and assembly technology out of the critical path to product development and TTM. Benchmarked and Qualified 0.35mm ball pitch Thin WLCSP Technology for Apex Enyo Module. Provided advanced technical leadership to significant design teams, technical review teams or problem resolution or cost reduction teams. Supported Package Technology Roadmaps definition. Served as Customer Technical Liaison: USA, Philippines, Korea, Taiwan, China, Malaysia & Japan. Technical Liaison for various Multi-Chip Product Co-Product Development/Partnerships Programs with Vishay, AOS, Primarion, Fairchild, etc. Resolved QPL High Density Lead Frame Array (HLA) technology adoption barrier (System in Package Solder Leakage). Enabled Pb-Free SIP / Power Modules product development. Supported Supplier & Subcontracts Management: Amkor, ASE, Unisem, Carsem, UTAC, UDG. Granted 15 US Patents.
EDUCATION
Rochester Institute of Technology
Masters of Science in Mechanical Engineering, Thermal Sciences
University of Puerto Rico-Mayaguez
Bachelor of Science in Mechanical Engineering, Thermal Sciences
SKILLS
ABOUT RANDOLPH CRUZ
Program / Project Manager with 10+ years of experience in microelectronic packaging and engineering roles. Strategic and innovative thinker with proven track record of leading and executing complex projects. Granted 19 US Patents. Qualified and production ramped of over products without an incident of delay in market release schedule due to packaging/assembly related issue. Experience designing advanced packages for Multi-Chip, DrMOS, Smart Integrated Power Stages and Power Modules / System-in-Packages such as:o Quad Flat No-Lead (QFN)-6mmx6mmx1mm package with Dual Cu Clip interconnects.o Stacked-Die Flip Chip-On-Lead (FCOL) QFN-5mmX7mmX1.5mm package.o Dual-Exposed QFN-5mmX5mmX0.6mm package with FCOL and Cu Clip interconnect.o Stacked-Die QFN-5mmX6mmX1mm QFN package with Cu Clip interconnect.o High Density Lead Frame Array (HLA) 17mmX19mmX3.5mm package.o 0.40mm Pitch Thin Wafer Level Chip Scale Package 4.040mmX4.040mmX0.400mm, 81 Ball.o 0.35mm Pitch Thin WLCSP 2.439mmX2.439mmX0.364mm, 36 Ball.
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