Ran Zhao
Lead Application Engineer @Cadence
Lyon, FR
EMAILS
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Sep 2021 — Present
Lead Application Engineer @Cadence
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Grenoble, FR
EDUCATION
2008 — 2010
Paris-Sud University (Paris XI)
Master, Electronic systems for signal processing(SESIS)
2000 — 2004
Tongji University
Bachelor, Information Engineering
SKILLS
MakefileVerilogFpgaVhdl/Vhdl-AmsVhdlSocInstrumentationC/C++Microsoft Office (Excel, Word, Powerpoint, Visio, Project)Unix, Linux, WindowsSystemcNcsimSystemverilogUvmXilinx Ise, QuartusEmbedded SystemsTeam ManagementSignalMatlabArmLab EquipmentsTrace32 DebuggerSvn, Clearcase, SynchronicityDigital Signal/Image ProcessingJtag, Rs-232, Arinc429, Can, I2cAssembly Language(Dsp T1 C6x, Arm, Mips)Modelsim, Cve, Ncsim, Vcs, Novas
ABOUT RAN ZHAO
Experienced verification engineer with a demonstrated history of working in ASIC and FPGA development. Strong knowledge in TLM verification(UVM, SystemC), SystemVerilog, Signal processing, System on a Chip (SoC), and FPGAs.
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