Ramya Srinivasan
Design Enablement Architect @ GlobalFoundries
- Role
- Pmts Design Enablement Methodology at GlobalFoundries
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Ramya Srinivasan
20 years of experience in back-end design and implementation using automated RTL to GDS flow.ISO 26262 CertificationExperience in setting up methodologies for static timing (Gate and transistor level), formal verification, and reliability verification for cell based designsExperience in working on new design challenges in the 14nm process node with FinFETs ASIC physical design implementation on media SOC\'s blocks using Synopsys tool suites Experience in performing due diligence during design phase and working closely with vendors.Worked in multi-discipline, geographically dispersed teams. Able to balance technical, operational and business needs.
Experience
Pmts Design Enablement Methodology
Mar 2025 — Present · US
Design Enablement Architect - EMIR and STAEDA Partnerships - Program Manager- Operations, Strategy and DRC/LVS PDK decks3DIC Flow Development
Education
Sri Venkateswara College of Engineering, Sriperumbudur, India
Bachelor's Degree, Electrical and Electronics Engineering
1996 — 2000
San José State University
M.S Electrical Engineering, EE
2002 — 2004
San José State University
M.S, Electrical Engg
2002 — 2004
Skills
- Asic
- Soc
- Debugging
- Embedded Systems
- Rtl Design
- Verilog
- Semiconductors
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