Ramesh Babu Chintala
ASIC/RTL Design Engineer | IIT Hyderabad | Hokkaido university, Japan
- Role
- Staff Engineer at Samsung Semiconductor
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Ramesh Babu Chintala
Hi,I\'m currently working as ASIC Digital Design/RTL Design Engineer in Synopsys on 112G Ethernet IP. My role includes behavior modelling of Analog blocks for digital simulations, RTL Coding for Transmitter, Spyglass LINT/CDC, and Synthesis.Prior to working in Synopsys, I have worked in Xilinx as verification engineer in DDR4. My role includes running regression, debugging, and coverage analysis.I have done my M.Tech in Microelectronics & VLSI from IIT Hyderabad after completing my B.Tech in Electronics & Communications engineering from RGUKT Basar(well known as Basar). During M.Tech at IITH, I have worked on various analog and digital projects.I was awarded A+ grade for my M.Tech thesis for outstanding performance in research.Expertise: Modelling and verification languages: Verilog, Systemverilog & UVMTools: Verdi, Xilinx ISE, Cadence spectre, Cadence virtuoso, OrCad, and EAGLE ASIC & FPGA design flow, Static Timing Analysis (STA), Design verification
Experience
Staff Engineer
Apr 2025 — Present · Bengaluru, IN
Education
Indian Institute of Technology Hyderabad
M.Tech (Research), Microelectronics & VLSI
2017 — 2020
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