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Ramesh V

Senior Pre-Si validation engg

Role
Pre-silicon Verification at Intel
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

About Ramesh V

Objective: To Explore VLSI Design - ASIC Design & Verification Specialties: HDLs:…

Experience

  1. Pre-silicon Verification

    Intel

    Aug 2024 — Present · Bangalore, IN

Education

  • Govt college of Engg - Bargur , Anna university

    B.E, ECE

    2004 — 2008

  • College Of Engineering, Guindy - Anna university

    M.E, Applied Electroncs

    2008 — 2010

Skills

  • Logic Synthesis
  • Vlsi
  • Perl
  • Eda
  • Integrated Circuit Design
  • Gnu Debugger
  • Open Verification Methodology
  • Vhdl
  • Asic
  • Systemverilog
  • Rtl Design
  • Usb
  • Rtl Coding
  • Verilog
  • Veritas Cluster Server
  • Amba Ahb
  • Modelsim
  • Functional Verification

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Ramesh V — Pre-silicon Verification at Intel in Bengaluru, KA, IN | Unifers