Ramesh Sukumar

About Ramesh Sukumar

Skilled Senior Engineer with 8+ years of experience in RTL/FPGA design and development.I have a proven track record of enhancing QOR for Vivado implementation flows on synthesis, PnR flow improvements, analyzing customer dcp\'s for timing closure and resource optimization.Expertise in synthesis, CDC, STA, timing closure, ECO and FPGA design for embedded, signal processing, communication, and defense & aerospace applications, with hands-on experience on Versal, Ultra scale FPGA\'s.I am proficient in Verilog/VHDL/System Verilog, TCL, and possess a working knowledge of various protocols (SPI,I2C,URART,PCIe,JESD204B etc.) and tools (Xilinx Vivado, VCS, onespin etc.). and good understanding of AMBA bus protocols (AXI, AHB, APB). Now currently expanding skills in Python.

Experience

1. Senior Engineer

   AMD

   Nov 2022 — Present · Hyderabad, IN

Education

• Dhanalakshmi college of engineering

  Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

  2012 — 2016

Skills

• Leadership
• Microsoft Office
• Management
• Project Management
• C
• Teamwork
• Microsoft Word
• Strategic Planning
• Microsoft Excel
• Powerpoint