Ramesh Ramalingam

About Ramesh Ramalingam

About 19 years of experienced Physical Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Place & Route(Floorplan, Powerplan, CTS and Routing), Timing Closure, STA, ECO generation and Implementation, Design Rule Checking (DRC), EDA, Layout Versus Schematic (LVS), and Power Analysis. Strong engineering professional with a Master of Engineering in Applied Electronics focussed VLSI Design from College of Engineering Guindy, Anna University, Chennai. Successfully streamed out 20+ fullchips across all the foundries in the world. Foundries worked are TMSC,UMC,SMIC,DongbuHitech, ATEML and XFAB,

Experience

1. Senior Manager - Physical Design

   Microchip Technology Inc.

   Jan 2024 — Present · Chennai, IN

   The Roles and responsibilities are: Technical management of medium to big size teamSetting the delivery goals to the team.Resource management based on the current criticality of the projectInteracting with multiple team like Design/Synthesis/STA/DFT and Product EngineerGuiding Leads to solve the problems

Education

• Thiagarajar College of Engineering, Kamaraj University, Madurai.

  BE, Electrical and Electronics

  1999 — 2003

• College of Engineering Guindy, Anna University, Chennai

  ME, Applied Electronics

  2004 — 2006

Skills

• Clock Tree Synthesis
• Static Timing Analysis
• Primetime
• Eda
• Rtl Design
• Soc
• Asic
• Low-Power Design
• Verilog
• Timing Closure
• Physical Design
• Tcl
• Physical Verification
• Vlsi
• Lvs
• Ic
• Drc