Ramesh Pavuluri
RTL Design Engineer
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ramesh Pavuluri
Experienced RTL Design Engineer skilled in microarchitecture design, Verilog/System Verilog coding, timing analysis, and logic synthesis. Expertise in developing IPs like SPI, APB, AHB, and MIPI-UniPro, with strong knowledge of integration, LINT, CDC, and synthesis. Expertise in ISO26262, Functional Safety (FuSa), ASF & RAS feature development in PCIe Gen5 and Gen6.
Experience
Lead Design Engineer
Jan 2026 — Present · Bengaluru, IN
Education
Tirumala Engineering College
Bachelor of Technology - BTech, Electronics and Communications Engineering
2014 — 2018
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