Ramesh Byra

Physical Design Intern @Sumedha Institute Of Technology

Hyderabad, IN

Project 1 : Block level implementation Technology : 28nm• Validated sanity checks on synthesis and did Floorplan, placement, cts, routing• Resolved congestion issues by creating placement blockages & bounds in the placement stage.• Performed LVS checks and cleared opens and shorts in routing stage.• Performed various sanity checks on sta inputs and generated reports. Fixed setup and hold violations and some drc fixes using various methods.• Delivered timing clean blocks considering all scenarios.Project 2 : Block level implementationTechnology : 28nm• Loaded Verilog RTL file and standard cell libraries into the dc_shell.• Applied timing and constraint files (SDC) to the design for accurate timing analysis and optimization.• Performed RTL elaboration to generate an intermediate design representation for further synthesis.• Ran synthesis commands to convert RTL into a gate-level netlist using the appropriate technology library.• Optimized the design by addressing logic optimization and resolving issues related to timing.• Generated the final gate-level netlist for further design steps, ensuring the design adhered to the provided specifications.

Aditya Engineering College

B.tech

Aditya Engineering College

Bachelor of Technology - BTech