Ramees Abdurahiman M

About Ramees Abdurahiman M

As an associate, I worked as IP/SOC Design Verification engineer, on ORAN-5G BFP Compression and SOC-I2CAs an Arm Consultant, I collaborated with the team lead to execute CPU IP functional stress verification for various ARM AE cores(AE-Automative Enhanced), ensuring robust communication interfaces and safety features. I leverage my expertise in HDL/HVL, verification methodologies, and protocols to debug fails, automate sanity runs, and enable changes to scripts for CI/CD of regressions.I have a strong educational foundation in Electronics and Communications Engineering, with a BTech degree from TKM College of Engineering and a VLSI Design Verification course from Maven silicon Bangalore.I have worked on Verilog, SystemVerilog, UVM, and SVA, and learned about simulation, synthesis, and FPGA/ASIC design flow. I am passionate about learning new technologies, software packages, and tools for use in projects, and I enjoy working with other designers and engineers to identify and alleviate errors and inefficiencies.

Experience

1. Senior Design Verification Engineer Consultant

   AMD

   Feb 2025 — Present · MY

Education

• Maven silicon Bangalore

  VLSI Design Verification course(Front End)

  2019 — 2020

• TKM College of Engineering , Kollam

  Bachelor of Technology - BTech, Electronics and Communications Engineering

  2014 — 2018