Rambabu Koppadi

About Rambabu Koppadi

Experience in physical design implementation from Floorplan, Placement, CTS and Routing-> Worked as DP/FP owner for subsystems on standard protocol SS-> Worked as full chip/SoC level PDN Lead-> Have working experience on resolving UPF related and FEV related challenges-> Handled multi-voltage blocks with many power domains and voltage areas-> Have handful experience on ECO implementation for timing critical blocks-> Handled soc\'s, subsystmes, tiles and partitions for EM/IR/SH/ESD closure-> Have experience in Dynamic/Static/Tide RV flow methodology-> Handled timing (setup and hold) critical blocks and SS\'s-> Handling bump connectivity and Analog net extractions at SOC level-> Had RV tools experience on Redhawk/Redhawk-SC/Voltus/Totem-> Understanding the ESD clamp requirement for SOC level-> Handling partitions/SS for power targets (PTPX)-> I have experience from RTL synthesis to PNR implementation-> Specialized in RTL synthesis and its challenges-> Have experience in DC-Topo/ICC2/FC-Compiler/StartRC/Primetime/VCLP/Conformal(FEV)/Innovus/Tempus/Qrc tools-> Have experience on Handling multi voltage blocks and high frequency blocks-> Scripting languages Shell,TCL,PERL and Python.

Experience

1. Lead Engineer

   Cadence

   Nov 2023 — Present · Bengaluru, IN

Education

• Z.P.H school Antarvedi

  SSC

• Vardhaman Collage of Engineering, Hyderabad

  Bachelor's degree

  2012 — 2015

• Govt. Institute Of Electronics, Secundrabad (GIOE)

  Special Diploma In Electronics

  2008 — 2011

Skills

• On Chip Variations
• Finfet Technology
• Static Timing Analysis
• Prime Time
• Linux
• Design Rule Checking (Drc)
• Digital Circuit Design
• C
• Perl
• Tcl
• Vlsi Basics
• Cadence Encounter
• Oracle Enterprise Linux
• Clock Tree Synthesis
• Asic Flow
• Routing and Optimization
• Icc Compiler
• Cadence Innovus
• Pnr Flow
• Netlist to Gds2
• Microprocessors
• Physical Design
• Floor Planning and Placement
• Verilog
• Application-Specific Integrated Circuits (Asic)