Hanumath Ramasarathi Mulukutla
Engineer, Senior Staff/Manager at QualcommSoC DFT Lead, silicon bringup, PSE
- Role
- Senior Staff Manager at 高通
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Hanumath Ramasarathi Mulukutla
Worked on the following DFT activities:* SSN ATPG, sims & Diagnosis.* Ijtag implementation for controlling blocks with SIB.* Development of ICL and PDL for entire SoC to bring up ATPG modes.* MBIST insertion, validation, Memory Repair Analysis.* Scan Insertion - pre & post design rule checks (DRC).* Logic BIST insertion & verification by simulations.* Formal Verification.* ATP Generation stuck-at, TDF, Cell Aware, hold sensitive patterns, Coverage Analysis & Pattern Simulations.* Test mode Constraints Validation/Analysis.* Implemented ECO\'s on PD netlist using Verdi.* Silicon Bring up -> pattern delivery, pattern failure analysis, yield analysis.* HTOL debug* Shmoo hole debug.* Managing a team of 5 & driving SOC DFT.* Can write small scripts in TCL, making progress to sharpen scripting skills.
Experience
Senior Staff Manager
Nov 2024 — Present · Hyderabad, IN
Education
Sathyabama University
B.E, Electrical & Electronics Engineering
2004 — 2008
University at Buffalo
Master of Science, Electrical/Electronics Engineering
2008 — 2010
Skills
- Atpg
- Static Timing Analysis
- Formal Verification
- Drc
- Clp
- Testing
- Cadence
- Simulations
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