Ramarao Yekkaladevi
Senior Staff Engineer @Qualcomm
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WORK HISTORY
Senior Staff Engineer @Qualcomm
Santa Clara, CA, US
Subsystem timing lead (ddrss) for Snapdragon mobile processor series.Pipeline planning/placement guidelinesFmax closure across performance corners in different modes (func/shift/capture)Timing closure (setup/hold/TDRC) across all signoff corners (300+)Constraints development and integration at SoC levelInterface timing closure for high performance clocks (IO Budgets, latency/skew checks)Physical aware ECO generationDCD/ADCD Closure for high performance clocks (default/EOL spec) PGV Flow/X-corner flow development.
EDUCATION
Harvard Business School Online
Other; Certificate of Specialization in Finance and Accounting
Andhra University
B.Tech, Electrical and Electronics Engineering
Indian Institute of Technology, Madras
M.Tech, IIT Madras , Chennai, MicroElectronics/VLSI Design
SKILLS
ABOUT RAMARAO YEKKALADEVI
Over 20+ years of Physical Design Implementation/physical verification/timing signoff experience taping out very large, complex chips for Mobile, Graphics, Networking, Server and PHY applications• Hands on expertise in Taping out designs at 3nm, 4/5nm, 7nm, 16/14nm, 20nm, 28nm• Timing Constraints Development and Integration• Methodology development, flow setup, automation• Floorplan, Powerplan, Placement, clock tree synthesis, routing • Correlation experiments to close gap between implementation and signoff tools in advanced technology nodes.• Clock Tree Specifications for complex clocking schemes• Full Chip Timing Analysis, ECO generation, Timing closure• Signoff leakage recovery and area optimization• Power Estimation and IR Drop Analysis• Multi-mode lib generation in different timing corners• Expertise with Complex IPs such as USB,DDR, PCIe PHYs• Expertise with Synopsys and Cadence Tool flows• Lead ASIC Implementation for highly complex designs• Customer Interface, Business Support and Technical PresentationsSpecialties: Synthesis, Floorplaning, Placement, Clock Tree Synthesis, Routing, Sign-off Timing closure, DRC/LVS/ERC
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