Ramamohan Reddy Nara

About Ramamohan Reddy Nara

Verification lead with 15+ years of industry experience in SOC/ASIC design and verification.• Proven expertise in various pre-silicon verification activities like test-bench definition, creation, constraint random stimulus and test generation, SV assertions, coverage driven verification, IP-SoC integration and collaboration with multiple teams in executing the verification plan. Experience in bare metal FW development, FPGA/HAPs proto typing, Emulation debug, post-silicon bring up planning, debug and execution. Experience with industry standard protocols like PCIe, DDR3/2, USB3.0/2.0, OTG, SD/SDIO/eMMC, ONFI, OCP, AXI, AHB and Ethernet protocols.• Experience with verification methodologies UVM, OVM and VMM.• Part of 15 successful multimillion gates ASIC/SOCs tape outs.• Experience with the gate level timing simulations, formal verification and Static timing analysis.• Work experience in India and US cross site projects execution and have good communication skills.SKILLS: • Protocols: PCIe, USB3.0, USB2.0, OTG, SD/SDIO/eMMC, DDR2, DDR3, ONFI, OCP, AXI and AHB• Languages: Verilog, SystemVerilog, python, C, C++• Verification Methodology: UVM, OVM and VMM• EDA tools: Simulators ModelSim and VCS, Formal Verification tool LEC, Static timing analysis using PT, Synthesis tool Simplify.

Experience

1. Design Verification Lead Manager

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   Apr 2019 — Present · Menlo Park, CA, US

Education

• Sri Venkateswara University, Tirupathi

  BTech, Electrical, Electronics and Communications Engineering

• Indian Institute of Technology, Bombay

  Masters, Micro Electronics and VLSI design

Skills

• Very-Large-Scale Integration (Vlsi)
• Soc Design Verification
• System on a Chip (Soc)
• Soc
• Systemverilog
• Python
• Silicon Debug
• Formal Verification
• Vlsi
• Open Verification Methodology
• Application-Specific Integrated Circuits (Asic)
• Perl
• Debugging
• Uvm
• Networking
• Vmm
• Rtl Design
• C
• Asic
• Functional Verification
• Ovm
• Static Timing Analysis
• Verilog
• Syetem Verilog
• C++