Ramachandrarao Parise

About Ramachandrarao Parise

Engineering professional with a Master’s degree in Electrical & Computer Engineering and 15 years of experience in semiconductor design driving timing convergence and physical design from RTL to GDSII across advanced nodes (2nm to 180nm). Proven track record of 22+ tape-ins with 100% silicon success, delivering high-performance, power-efficient SoCs for flagship chipsets. Adept at scaling engineering teams, fostering innovation, and aligning cross-functional stakeholders to execute complex programs under aggressive schedules. Recognized for strategic thinking, early debug culture, and unwavering execution across fast-paced environments.• Established and scaled engineering teams and workflows from ground zero, with strategic resource planning and streamlined processes aligned to aggressive tape-out schedules.• Led a multidisciplinary team of 18–20 engineers across Physical Design and STA, nurturing technical talent and driving performance through mentorship and accountability.• Strategic Thinking: Drove design/signoff trade-offs, defined technical direction.• Spearheaded innovative design closure strategies, leveraging deep knowledge of timing, constraints, and architecture for multiple complex SoCs and subsystems.• Crafted timing constraints for large-scale SoCs with over 250 clocks, optimizing for speed, power, and area across diverse product lines.• Achieved full-chip timing closure for hierarchical designs exceeding 400M gates, successfully meeting tape-out milestones in fast-paced environments.• Championed early-stage debug culture, identifying and resolving critical design bottlenecks during architecture and RTL convergence phases.• Cross functional collaborations with Design, DFT, PD, PV, FV, CLP & Dtech/Methodology teams.• Known for being agile, hands-on, and execution-focused, consistently stepping into high-stakes scenarios and delivering outcomes across cross-functional domains.• Proven ability to build and scale high-performing engineering teams from the ground up, leveraging deep technical expertise and strategic planning.Specialties:1) Proactively identifying the most effective and feasible solutions in real-time for any emerging issues.2) Anticipating critical issues early to ensure seamless project sign-off while optimizing design for the best possible PPA outcomes.3) Supporting cross-functional teams as needed, while consistently fulfilling core responsibilities.4) Fostering a healthy team environment by promoting a culture of openness and collaboration.

Experience

1. Srstaff Eng Mgr

   Qualcomm

   Dec 2022 — Present · Bengaluru, IN

   Handled Cores Timing Signoff in few of the projects & Currently responsible for Premier Tier SoC Tiles Timing/Signoff.

Education

• Nalanda Junior College

  High School, MPC

  2005 — 2007

• Vellore Institute of Technology

  Bachelor's Degree, ECE

  2007 — 2011

• Illinois Institute of Technology

  Master of Science - MS, Electrical and Computer Engineering

  2016 — 2018