Ramachandran Rajendran
Sr. Silicon Design Verification Engineer @Google
- Role
- Senior Silicon Design Verification Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Senior Silicon Design Verification Engineer
Sep 2025 — Present · Bengaluru, IN
Education
SVCE
Bachelor of Engineering (BE)
2008 — 2012
Skills
- Uvm
- Sv
- Fpga Verification
- Ovm
- System Verilog
- Very-Large-Scale Integration (Vlsi)
- Verilog
- D0-254 Process
- Field-Programmable Gate Arrays (Fpga)
- Perl
- Linux
- Systemverilog
- Testing
- Vhdl
- Debugging
- Fpga
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