Tripathi
Electronics Nerd | ASIC • FPGA • PD | Reliance Foundation Undergraduate Scholar
- Role
- Physical Design Trainee at Bharat Ic
- Location
- New Delhi, IN
- LinkedIn followers
- 500 followers
About Tripathi
Ram Tripathi, completed his high schooling from Kendriya Vidyalaya. And is currently…
Experience
Physical Design Trainee
Aug 2025 — Present
Gained end-to-end exposure to ASIC RTL-to-GDSII flow including floorplanning, placement, CTS, routing, STA, poweroptimization, and signoff.– Hands-on training with industry-standard EDA tools: Cadence Innovus, Genus, Tempus, and Synopsys IC Compiler II,PrimeTime.– Worked on congestion analysis, timing closure, IR-drop analysis, parasitic extraction, and DRC/LVS debugging.
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