Narayanasamy

About Narayanasamy

Innovative, versatile and team oriented Design Verification Lead & Engineer with 19+ years experience in Pre & Post silicon Functional Verification, Emulation, Testbench architecture and Implementation of Verification methodologies. Worked on 12+ highly successful A0 SoC, ASIC designs that has provided products with excellent functionality in several applications. Skills : Emulation, Design Verification activities, project planning, schedule & execution, collaboration with cross functional team, establish vendor relationship, multi-tasking, learn, guide, assist & mentor team, proven interpersonal and communication skill, always a team playerVerification: Sub system & SoC UVM-SV testbench, SV DPI-SystemC testbench, gate level simulation (unit level & timing), power verification using CPF, formal verification (ABV), verification & test plan creation, testbench architecture, UVM RAL implementation, RTL debugs, firmware.DV Domains: ARM SoC, Processor sub-system, Ethernet & PCIe sub-system, Coherent Ethernet DSP SoC, AVS SoC, Low power designs, power management, Ethernet Physical layer (PCS, PMD).Emulation: Simulation acceleration (TBX) using Veloce, Virtualab Ethernet, vProbe, Post-silicon validation.Protocols: Ethernet, PCIe, ACELite, AXI, AHB, APB, SPI, I2C, MDIO, UART, GPIOTools: Cadence Xcelium, Simvision, vManager, Siemens Veloce/Strato+, Questasim, Visualizer Coding Languages: UVM, System Verilog, Verilog, SVA, Python

Experience

1. Soc Verification

   Arm

   Nov 2024 — Present · Austin, TX, US

Education

• Thiagarajar College of Engineering

  Bachelor of Engineering (B.E.), Electronics and Communications Engineering

  2001 — 2005

• Vellore Institute of Technology

  Master of Technology (M.Tech.), VLSI Design

  2005 — 2007