Krishnamurthy

Experience

1. Component Design Engineer

   Intel

   Jun 2009 — Present

   RTL Design, simulation test, synthesis, test planning, execution, debug, lint check, Clock domain crossing check, analyze timing, formal verification, FV debug, floor planning, routing, timing driven placement, pre and post layout timing analysis and validation, back-end analysis and optimization of a wide variety of logic circuits/functions for Atom based SOC’s.

Education

• University of Colorado Boulder

  Master of Science (M.S.), Electrical and Electronics Engineering

  2002 — 2004

• University of Madras

  Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

  1998 — 2002

Skills

• Functional Verification
• Asic
• Intel
• Microprocessors
• Logic Synthesis
• Vhdl
• Verilog
• Soc
• Processors
• Low Power Design
• Perl
• Semiconductors
• Debugging
• Simulations
• Static Timing Analysis
• Computer Architecture
• Vlsi
• Rtl Design
• Systemverilog
• Tcl
• Low-Power Design
• Ic