Kishore. K
Aspiring RTL Design Engineer || VLSI Enthusiast || Verilog || Digital Design || EDA Tools
- Role
- Rtl Design Engineer at Vlsi First
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Kishore. K
K.RamkishorI am a recent B.Tech graduate from JNTUGV with a strong passion for Core related, throughout my academic journey.I am eager to apply my knowledge, learn from industry professionals, and contribute meaningfully to an organization.
Experience
Rtl Design Engineer
Aug 2025 — Present · Hyderabad, IN
Designed and implemented a 10 GB Ethernet MAC core compliant with 802.3ae standards* Focused on Verilog-based RTL development, transmit/receive data paths and protocol compliance.
Education
Avanthi Institute of Engineering & Technology
Diploma of Education, Electrical, Electronics and Communications Engineering
2019 — 2022
JNTU Gurajada Vizianagaram
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
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