Gupta
SOC Logic Design Engineer@Intel Corporation || Ex-Synopsys || Ex -Perfectvips || VLSI @CDAC || B.Tech @Electronics # Verilog | SV | UVM | Python | Perl | Shell Scripting | HTML
- Role
- Soc Logic Design Engineer at Intel
- Location
- Lucknow, UP, IN
- LinkedIn followers
- 500 followers
About Gupta
Highly motivated Experienced front end Verification Engineer in with 6+ years of experience in the VLSI semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Application-Specific Integrated Circuits (ASIC), System Verilog,Verilog, FPGA, Perl, and Shell Scripting. Worked on high end customer delivery with high quality verification Environment. Hands on Experience in writing the SV & UVM Test bench from scratch and debugging, creating test plan, verification plan, Experience in verification sign off with CRV, Assertion based, coverage based Verification methodology. Hands on experience in coverage and assertion based verification and having experience in industrial protocol PCIe TL, MIPI MPHY, Unipro & UFS Subsystem, UCIE-A protocol.
Experience
Soc Logic Design Engineer
Aug 2024 — Present · Bengaluru, IN
Education
Raj Kumar Goel Institute of Technology, Ghaziabad
B.Tech
2013 — 2017
CDAC Pune
PGDVLSI
2017 — 2018
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