Rakshith G N
Analog Layout Designer at IBM
- Role
- Lead Analog Layout Designer at IBM
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Rakshith G N
Experience : • Experience in handling SERDES PHY, PCIE Analog layout design blocks such as TX-LDO, op-amp, Current Mirror, Bias blocks, power gate and custom digital cell layout designs. • Experience on block level placement, Routing, Physical verification checks etc. • Strong exposure on Analog matching techniques, elimination of latch-up, shielding, area optimization, EM, SH, IR drop and RV issues. • Experience in Deep sub micron technologies like TSMC 3nm, TSMC 5nm, Intel 7nm, 10nm,14nm. • Good experience in Physical verification areas like DRC, LVS, ERC, Antenna checks. • Tools Exposure: Cadence Virtuoso EXL, XL and L, Schematic Editor, CPDS for Physical Verification. ….Thanks & Regards…. Rakshith G N Email- r••••••••@gmail.com Direct :+91••••••••04
Experience
Lead Analog Layout Designer
Oct 2024 — Present · Yelahanka, IN
Education
Visvesvaraya Technological University
Bachelor's degree
2013 — 2017
Seshadripuram First Grade College (S.F.G.C), Bengaluru
Pre university
2011 — 2013
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