Rakhil P

About Rakhil P

Low power VLSI RTL Design Verification engineerStrong skills in VLSI Verification with SV, UVM environmentGood knowledge in UVM RAL based verificationGood knowledge in GLS, PA GLS verification and debug skillsBasic understanding on PA RTL concepts on UPFBasic knowledge on python, tcl, perl and shell scripting languagesBasic Knowledge in C, C++, System Verilog, ASM conceptsGood command over Linux commandsBasic understanding on Makefile conceptsGood knowledge in usage of EDA tools of Synopsys VCS, DVEDomain Knowledge in FPGA implementation in Lattice, Xilinx and Altera FPGA’sGood knowledge in Hardware circuit design and post silicon validationSound skills in RTL design using Verilog HDL Sound abilities in digital circuit designProfound leadership and communication skills

Experience

1. Low Power Design Verification Engineer

   Google

   Jun 2024 — Present · Bengaluru, IN

Education

• Kendriya Vidyalaya keltron nagar

  Computer Science

  2004 — 2010

• Mar Athanasius College of Engineerng (MACE)

  M tech, VLSI & Embedded systems

  2014 — 2016

• Jawaharlal College of Engineering and Technology (JCET), Ottapalam

  B tech, Electronics & Communication

  2010 — 2014

Skills

• Microsoft Office
• C
• Vlsi
• Embedded Systems
• C++
• Matlab
• Embedded C
• Verilog
• Leadership
• System Verification
• Vlsi Cad
• Xilinx Ise
• Orcad
• Pspice
• Arm Cortex-M
• System Verilog
• Lattice
• Fpga
• Altera Quartus