Rakesh Ujjawal
SoC Design & STA Engineer
- Role
- Sr Manager, Silicon Design Engineering at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Rakesh Ujjawal
18 years of experience in VLSI industry in STA, Constraints development, IO timing…
Experience
Sr Manager, Silicon Design Engineering
Jan 2025 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master’s Degree
2014 — 2015
Dr. A.P.J. Abdul Kalam Technical University
Engineer’s Degree
2001 — 2005
Skills
- Rtl Coding
- Systemverilog
- Fpga
- Rtl Design
- Static Timing Analysis
- Verilog
- Functional Verification
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