Rakesh Siddhartha Nagineni
Power Performance Area Design Engineer
- Role
- Power Performance Area Design Engineer at Intel
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Rakesh Siddhartha Nagineni
Good working knowledge of Linux, shell scripting Worked on Multi Power Domains…
Experience
Power Performance Area Design Engineer
Jul 2022 — Present · Hyderabad, IN
Education
Bhashyam high school, RK puram, Hyderabad
S.S.C
2008 — 2009
RV VLSI Institute - Bangalore
Advanced PG diplamo in ASIC design
2016 — 2016
E V M College of Engineering & Technology, Jonnalagadda, Narasaraopet-522601(CC-AR)
Bachelor of Technology (B.Tech.)
2011 — 2015
Skills
- Static Timing Analysis
- C
- Perl
- Eda
- Asic
- Linux
- Physical Design
- Tcl
- Application-Specific Integrated Circuits (Asic)
- Integrated Circuit Design
- Cmos
- Very-Large-Scale Integration (Vlsi)
- Ic
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