Rakesh Rakesh S Shankaraiah

About Rakesh Rakesh S Shankaraiah

Analog / Mixed-Signal Layout Design Engineer with 5+ years of experience in full-custom CMOS layout for AMS and SoC designs. Strong expertise in Cadence Virtuoso, LVS/DRC closure, parasitic-aware layout, and device matching techniques. Proven contributor to multiple tape-outs with a focus on performance, manufacturability, and layout robustness. Passionate about advanced analog layout challenges and continuous technical growth toward Senior/Lead roles.

Experience

1. Senior Layout Design Engineer

   Phyelements Llp

   Nov 2023 — Present

   Expertise lies in precision layout techniques including common-centroid matching, interdigitization, shielding, guard rings, well isolation, and sensitive node protection to minimize noise, mismatch, and process variations. Strong emphasis is placed on robust power distribution through optimized power/ground grids and IR-drop aware routing.Extensive experience includes parasitic-aware layout, metal density compliance, electromigration (EM) checks, antenna rules, and DFM considerations to enhance yield and reliability. Close collaboration with circuit designers ensures successful closure of DRC, LVS, and PEX, along with iterative layout optimization for performance targets.The focus remains on delivering layouts that balance Performance, Power, and Area (PPA) while maintaining manufacturability, reliability, and technical leadership, including mentoring junior engineers.

Education

• PES College of Engineering, Mandya

  Bachelor of Engineering - BE, Electronic and Communications Engineering

• Srimath Polytechnic Mysore

  Diploma of Education, Electrical, Electronic and Communications Engineering Technology/Technician

• Jawahar Navodaya Vidyalaya - JNV

  10th Standard