Rakesh Pednekar
Principal Engineer | AMS Verification | Cadence Design Systems | MTech VLSI Manipal University | 6k+ connections
- Role
- Principal Enginner at Cadence
- Location
- Pune District, MH, IN
- LinkedIn followers
- 500 followers
About Rakesh Pednekar
Overall, 10 years of experience in the semiconductor industry.• Approximately 7 years of experience in the field of AMS modeling and digital mixed signal verification. It involves: Responsible for leading AMS verification activity with a team of 4 people, for RRAM 8Mb and 24Mb Memory and Test Chip IP’s. Setup AMS verification environments from scratch mostly in verilog and verilog-AMS. This is done in both Cadence and Synopsys Verification environments. Critical resource of the AMS verification team handling 112Gb and 60Gb SERDES IP’s. This involved Top level SERDES IP verification. Block Level verification was also done by developing Wreal models for Analog blocks and verify them against schematic behavior using Co-Sim methodology. Aided in developing behavioral RTL for digital IP’s and correlating them with unit delay GLS and SDF annotated GLS netlists. Contributed to USB 2.0 PHY IP Top Level AMS verification.• More than 3 years of experience in analog modeling and verification of power management blocks across various architectures and topologies with over 100+ components delivered independently. • Mentoring juniors technically. An enthusiastic and a fast learner
Experience
Principal Enginner
Apr 2024 — Present · Pune District, IN
Education
D. G. Ruparel College Of Science and Commerce
HSC, Science
2004 — 2006
Holy Cross Convent School, Mira Road, Thane
SSC, schooling
1992 — 2004
Manipal Institute of Technology
Master of Technology (MTech), Microelectronics(VLSI and Embedded)
2011 — 2013
University of Mumbai
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
2006 — 2010
Skills
- Fpga
- Asic
- Tispice
- Dc-Dc
- Microcontrollers
- Switchers
- Post Silicon Validation
- Soc
- Altera Quartus
- Analog Power Modelling
- Vlsi
- Power Converters
- Debugging
- Perl
- Quartus
- Rtl Design
- Modelsim
- Xilinx Ise
- Cadence Virtuoso
- Vhdl
- Verilog
- Pspice
- Simetrix
- System on a Chip (Soc)
- Ti Dsps
- Very-Large-Scale Integration (Vlsi)
- Xilinx
- Systemverilog
- Simplis
- C
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