Rakesh Paladugula
ASIC Physical Verification Engineer at Google
- Role
- Asic Physical Verification and Convergence Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Rakesh Paladugula
Good understanding of block-level, subsystem-level, and full-chip Physical Verification.Handled the full-chip LVS flow, adeptly resolving Flat and Bbox LVS issues. Implemented scripts that tackle DRC issues and crafting GUI utilities to enhance efficiency in manual processes.Good hands on experience in full-chip Physical Verification checks, covering DRC, Antenna, and Density. From floorplan conception to signoff, I\'ve overseen subsystems for PV closure, addressing critical aspects such as ESD and PERC.Engaging in full-chip floorplan activities, including pin placement, feedthru pin creation, repeater insertion, and analysis, and Provided guidance to Physical Design engineers, ensuring the resolution of Physical Verification issues and the seamless convergence of blocks.My hands-on experience extends to addressing layout PV issues and collaborating closely with block owners for systematic issue rectification through scripts and manual fixes. I handle tasks ranging from Oasis, netlist modification to base and metal fill insertion, and DRC/LVS flow setup.
Experience
Asic Physical Verification and Convergence Engineer
Apr 2024 — Present · Bangalore, IN
Education
Jawaharlal Nehru Technological University, Kakinada
Bachelor of Technology - BTech, Electronics and Communications Engineering
2014 — 2017
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