Rakesh Nandyala

About Rakesh Nandyala

13 years of work experience as a Micro-architect and RTL Designer along with hands on…

Experience

1. Design Engineer

   Tachyum

   Jan 2019 — Present

Skills

• C
• Schematics: Opus (in-House), a Wrapper Around Cadence Virtuoso, Cadence Icfb
• Simulations
• Verilog
• Chip Tester: Tektronix Lv500
• Timing: Prime Time, Tango (in-House) Equivalent to Primetime
• Static Timing Analysis
• Extraction: Scarlet (in-House) Equivalent to Starextraction
• Computer Architecture
• Validation: Mynx (in-House) (Mixed Signal Validation Tool), Synopsys Vcs
• Simulator: Presto (in-House) Equivalent to Spectre, Nc Verilog, Verilog Xl
• Programming Languages: System Verilog, Verilog, Verilog-Ams, Perl, Tcl, C, C++
• Ic
• Layout and Drc/Lvs: Genesys/Lvs (in-House) Equivalent to Caliber
• Cadence Virtuoso
• Mixed Signal
• Systemverilog
• Rtl Coding
• Logic Synthesis, Automatic P&R: Synopsys Design Compiler, Synopsys Ic Compiler
• Semiconductors
• Rtl Design
• Formal Verification: Fev (in-House) Equivalent to Cadence Conformal
• Ir Drop & Em Analysis: Rv (in-House) Equivalent to Redhawk
• Logic Synthesis
• Asic