Rakesh Misra
Director Of Engineering at Intel Corporation
- Role
- Director of Engineering at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Rakesh Misra
Experienced Engineering Manager with a demonstrated history of working in the wireless…
Experience
Director of Engineering
Dec 2019 — Present · IN
CPU tech leader/Director, SoC power architect involved across many cross functional teams with main responsibilities of understanding product, architectural requirements and providing technical feedbacks on design/PPA optimizations, Uarch development, generating design reference docs. Reviews of RTL & Testplans. Reviews & QC of functional/timing/power ecos,debugs. xPU (GPU+CPU) SoC Uarch understanding and development, proposals to next gen xPU products. Converged Coherent Fabric IP development -> Uarch, IDI protocols, Cache coherency protocols – MSI/MESI/MOESI/MESIF/MOESIF used across Client segments & Servers.Generated : scalable to generate non-supported configurations with all types of xactions.ADLN Client (laptop segment): Power arch,Uarch delivered SoC Power MAS ( Client SP)Detailed Visio of SoC Pwr rail mapping, Platform->SoC->Partition->HIP/SIP pwr conn.PG pin (HIP/AIP/SIP) conn checker & MPG<-MINI-pkg bumps->die bumps-> logic for ICC MAX per rail (Vnom),BI ICCMAX (BI ) Generated pwr up sequences, Boot,PKG C*/S* states given to SW teams. HVM/BI/TIU teams for tests and content development.Client (laptop SoC): Uarch reviews of multicore CPU sub-system involving four cluster quad Cortex A53,Boot, GIC, Timers, CPR, DTS.Int strategies. Pwr rail definitions, debug sub-system design. Reviewed all design aspects, DFD infrastructure. Testplans, testcases. debugs.Filed IDF that received Patent, Distinguished Invention Award ( Method and Apparatus of identify and validate highly critical non-resettable flops in the boot path in a Closed Chassis Sys) 24th May 2022.Received 15 recognition awards from cross-functional teams.
Education
Delhi College of Engineering
B.E.
1995 — 1999
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