Rakesh Landeri

Silicon Engineering Associate Manager (IC Layout Design & Automation Engineer ) at Accenture India .

Role
Silicon Engineering Associate Manager at 埃森哲
Location
Hyderabad, TG, IN
LinkedIn followers
500 followers

About Rakesh Landeri

Working as a IC layout engineer on 150nm,300nm,28nm,22FDX(22nm),14nm (Finfet), 11nm(Finfet),7nm,5nm (Finfet)nodes and Trained in SKILL,shell,PERL,TCL scripting languages,Python pragramming language and C programming language, Design Rule check(DRC), Layout versus schematic(LVS), Physical verification tools assura and calibre with 9 years of experience and Trained in Vedaiit on custom layout engineer.Schematic Generation using spice vision pro /spice in for TS28HPCP/UMC28HPCP.Abstract and Lef Generation using Abstract generator Analog Blocks: BGR,OP -AMP,Ring oscillator, LDO,Complex LDO blocks,Vref in receiver block in TS16nm,TS7nm and TS5nm.Skill Scripting for Flow Developments :Standard cell Library Checker( Half drc and guidlines checking)Nodes: 5nm,7nm,12nm,14nm,28nm,22nm,150nm-300nm.

Experience

  1. Silicon Engineering Associate Manager

    埃森哲

    Feb 2025 — Present · Hyderabad, IN

Education

  • Kakatiya High School

    Ssc, Electronics

    2005 — 2007

  • JNTUH College of Engineering Hyderabad

    Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

    2009 — 2013

  • Kakatiya junior college

    Intermediate, M.P.C

    2007 — 2009

  • S.T.JOHNS HIGH SCHOOL

    Primary

    2000 — 2005

Skills

  • Svrf
  • C
  • Programming
  • Cadence Virtuoso
  • Microsoft Office
  • Vlsi
  • Tcl-Tk
  • Matlab
  • Very-Large-Scale Integration (Vlsi)
  • Cmos
  • Unix
  • Easily Adaptable
  • Calibre Tools -QA
  • Physcial Verification
  • English
  • Perl
  • Public Speaking
  • Linux
  • Windows
  • Powerpoint
  • Microsoft Word
  • Skill
  • Quick Learner

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Rakesh Landeri — Silicon Engineering Associate Manager at 埃森哲 in Hyderabad, TG, IN | Unifers