Rakesh Kumar

About Rakesh Kumar

4 Years of experience as RTL Design engineer in Semiconductor Industry. Skilled in VHDL…

Experience

1. Silicon Design Engineer 2

   AMD

   Feb 2024 — Present · Hyderabad, IN

   Currently working in timing analysis team, where my task is to create verilog design (mostly design is clock related), write design constraints~>generate design check point (.dcp file) and timing reports(.rpt file). Once the timing reports are generated, analyse the delays, bel parameters.To speed up our task and automate few things, we use TCL and python scriptingI have also worked in DSV team where I was Involved in IP integrator of VIVADO

Education

• National Institute Of Technology Sikkim

  B.TECH

  2016 — 2020