Rakesh Kumar

About Rakesh Kumar

am a Lead Physical Design Engineer with 8+ years of experience in advanced semiconductor technology nodes (22nm → 5nm). My expertise lies in Place & Route (PnR), Timing Closure, Physical Verification (DRC/LVS), and Low-Power Design Enablement, with a strong track record of delivering multiple high-frequency SoC subsystems and successful tape-outs.At NXP and previous roles with Intel, ST, and MediaTek projects, I’ve: • Enabled multi-node technology transitions (22nm, 16FFC, 14nm, 10nm, 7nm, 5nm). • Automated PnR/PG flows, reducing runtime by 15% and improving utilization by 10%. • Delivered 20+ block-level and subsystem-level tape-outs (up to 2.5M+ cells, 40+ macros). • Partnered with EDA vendors (Synopsys, Cadence) and foundries to achieve first-time-right silicon.Core Skills: PnR • Floorplanning • CTS • Power Planning • Routing • STA • Flow Automation • DRC/LVS • Low-Power Design • Innovus • Fusion Compiler • Tempus • Calibre • Twiker • ParadeI thrive in cross-functional design enablement roles, providing technical leadership and mentoring while driving PPA (Power, Performance, Area) improvements. My goal is to continue contributing to cutting-edge SoC design and enablement at advanced nodes.Open to connecting with semiconductor professionals, hiring managers, and innovators in the VLSI ecosystem.

Experience

1. Lead Design Engineer

   NXP Semiconductors

   Sep 2021 — Present · Noida, IN

Education

• BBDIT,Ghaziabad

  Bachelor's degree

  2011 — 2015

Skills

• Research
• Modelsim
• System on a Chip (Soc)
• C
• Programming
• English
• Sta
• Training
• Microsoft Office
• Vlsi
• Physical Design
• Static Timing Analysis
• Digital Electronics
• Asic
• Clock Tree Synthesis
• Cadence Encounter
• Perl
• Powerpoint
• Photoshop
• Semiconductors
• Public Speaking
• Engineering
• Verilog
• Microsoft Word
• Electronics
• Team Management
• Windows
• Analog Circuits
• Tcl