Rakesh Doguparthi

About Rakesh Doguparthi

Career Interests - RTL Design/Verification SoC Design/Verification ASIC/FPGA Validation Digital Design Verification/Validation Hardware TestingTechnical skills - Languages: Verilog /VHDL C/C++ Python UVM/OVM SystemVerilog Tools Worked: Synopsys VCS Slickedit Cadence tools(Virtuoso,RTL Compiler,Spectre,Encounter)Vivado design Suite Mentor Graphics ModelSim Eclipse CodeblocksVisual StudioXilinx ISE MATLAB Atmel Studio Xilinx Vivado Design Suite 2014 Technical know-how - Extensive experience in understanding and working with CPU Architectures(Worked on DDRT and HBM Memory protocols) Vast experience and coding skills in Object Oriented Programming and Data Structures. Good understanding and experience in UVM/OVM methodologies for Testbench development. Excellent Verilog coding skills(Worked on increasing the test coverage for BFM in System Verilog(UVM) in VCS,did projects in SOC with FPGA). Healthy knowledge in ASIC flow: Design and Verification using Verilog and SystemVerilog. Excellent Debugging skills(Played with GDB, Totalview,Valgrind) Great Insights in understanding and working with FPGAs (Did Projects on Driver development, Game development)

Experience

1. Smts Hardware Engineer

   AMD

   Jul 2024 — Present · Austin, TX, US

Education

• Portland State University

  Master’s Degree, Electrical and Computer Engineering

  2014 — 2016

• Jawaharlal Nehru Technological University

  Bachelor’s Degree, Electrical, Electronics and Communications Engineering

  2010 — 2014

Skills

• C
• C++
• Verilog
• System Verification
• System Verilog
• Python
• Computer Architecture
• Ovm/Uvm
• Embedded C
• Linux
• Cadence Virtuoso
• Functional Verification
• Validation
• Java
• Microsoft Word
• Systemverilog
• Powerpoint
• Microsoft Excel
• Microsoft Office
• English
• Xilinx