Rakesh Amancha
Mixed Signal Logic Design Engineer at Intel Corporation
- Role
- Logic Design Engineer at Intel
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Rakesh Amancha
Areas of intereset :ASIC/FPGA RTL DesignSkills :Verilog, VHDL, C, ScriptingEDA Tools : Xilinx ISE, Xilinx Vivado, Altera Quartus, Modelsim, Cadence NCSIM, Cadence Incisive HAL, Mentor Questa CDC (0in), Cadence Conformal LECFPGA Experience :Spartan 3A DSP, Cyclone Cyclone IV, Virtex 6, Virtex Ultrascale
Experience
Logic Design Engineer
Jun 2020 — Present · Bengaluru, IN
Education
Manipal Institute of Technology
Masters, VLSI
2010 — 2012
Vignana Bharathi Institute of Technology
B.Tech, Electronics and Communication
2005 — 2009
Tejaswi High School
10th, Maths, Science, Social
2000 — 2003
Skills
- Shell Scripting
- Cadence Encounter
- Rtl Coding
- Linux
- Modelsim
- Low-Power Design
- Rtl Design
- Altera Quartus
- Verilog
- Eda
- Synopsys Dc-Synthesis
- Physical Design
- Vlsi
- Digital Design
- Xilinx Ise
- Systemverilog
- Vhdl
- Static Timing Analysis
- Fpga
- Asic
- C
- Digital Signal Processors
- Cadence
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