Rajul Amin

About Rajul Amin

20+ years of ASIC design verification experience including 10+ years as a verification Lead.• Proven Track record of delivering multiple successful ASIC chips as verification manager. • Experience of setting up and growing multiple verification teams and managing them through transitions.• Expertise managing global teams in US, Asia and Europe.• Proven ability to influence architecture & design tradeoffs to reduce verification complexity to improve predictability of schedule and Time to Market.• SoC Development experience in mobile, enterprise, consumer and solid state drive market segment.• Extensive experience in verification methodologies like UVM, OVM, SV Assertions and Emulation helps promote overall verification strategy to promote re-use and scalability.• Hands on experience in verification including simulation, Embedded C (FW/Use cases), Gate level sim (SDF), power aware simulation (UPF), Emulator (Palladium) and FPGA Prototyping (RPP).• Experience with design activities including RTL design, DFT, Synthesis, formal equivalence checking.• Worked with Firmware teams to develop FW architecture, boot flows and hardware interface layer.

Experience

1. Founding Member

   Vyavastai

   Mar 2025 — Present · Austin, TX, US

   Working on the Next Big Thing!

Education

• L. D. College of Engineering

  BE, Instrumentation Control

  1990 — 1994

• Gujarat University

  BE, Instrumentation Control

  1990 — 1994

• Arizona State University

  MS, VLSI Design

  1995 — 1996

Skills

• Debugging
• Systemverilog
• Rtl Design
• Vlsi
• Ic
• Soc
• Asic
• Embedded Systems
• Semiconductors
• Verilog