Raju Hp

About Raju Hp

Experience Summary insertion, scan compression, DRC analysis, low coverage analysis and pattern generation and simulation.MBIST Design implementation, synthesis and verificationJTAG test cases for mandatory and other test mode IR verification and simulation. Flash memory testing implementation of custom flash memory testing through JTAG port of SoC with SPI interface.Specialties: SoC DFT implementation, MBIST design, Flash memory testing, JTAG, verilog, perl, SED, AWK, Unix c-sehll scripting.Having experience on these TOOL \'s Simulation : ModelSim, NC-sim Synthesis : Design Compiler Scan Insertion : DFT-MAX, ATPG : TestKompress, Encounter Test Formal Verification : LEC Scripting : Perl, Cshell, SED, AWK, and GREP.Academics summary Completed Master degree in Embedded and Wireless Technology from Manipal University.Completed one year internship at STMicroelectronics.Internship Details - Project Title :\" To implement STIL based simulations of BOUNDARY SCAN for DFT Environment \" Role : • Responsible for BSD STIL patterns’ implementation & simulation, stuck at ault and transition fault ATPG STIL patterns’ simulation, OCC active STIL patterns’ simulation and sending to TE for an SoC for Leading Gaming console provider. • Additionally writing Perl script and Cshell script to generate test cases and to automate some part of the work.

Experience

1. Soc Design Engineer

   Intel

   May 2017 — Present · Bengaluru, IN

Education

• Manipal Institute of Technology

  Master of Science (MS)

  2010 — 2012

Skills

• Static Timing Analysis
• C
• Perl
• Embedded Systems
• Rtl Coding
• Soc
• Mbist
• Boundary Scan
• Verilog
• Shell Scripting
• Automatic Test Pattern Generation (Atpg)
• Ncsim
• System on a Chip (Soc)
• Electronics
• Atpg
• Perl Script
• Logic Design
• Dft
• Simulations
• Joint Test Action Group (Jtag)
• Jtag
• Unix Shell Scripting