Raju Gedda

About Raju Gedda

With over 13 years of experience in VLSI Front-End RTL and SoC design, I have developed strong expertise in multiple SoC architecture chassis and integration. I specialize in the design and microarchitecture of media IP. I possess deep knowledge of SoC clock microarchitecture and structural design, alongside hands-on experience in achieving SoC low-power design targets, battery life optimization, and balancing power and performance metrics.I collaborate closely with DFT, Physical Design, and both pre- and post-silicon debug teams to ensure robust chip functionality. Additionally, I have experience working on silicon packaging for stacked dies.I am the author of three technical papers, one paper currently under publication, and eight technical posters.

Experience

1. Soc Design Engineer

   Intel

   Nov 2018 — Present · Bengaluru, IN

   Led RTL design and integration for high-performance AI-enabled Client SoCs, focusing on scalability, low power, and timing closure- Drove power optimization (PnP) achieving ~15% reduction across critical subsystems (clocking, display, interconnect paths)- Designed and enhanced high-speed interconnect logic and protocol bridges enabling efficient IP-to-IP and die-to-die communication- Worked on multi-clock, multi-voltage domain designs, ensuring robust CDC and low-power (UPF-based) implementation- Delivered timing-closure clean RTL across complex pipelines with deep focus on QoR (PPA: Power, Performance, Area)- Performed lint, CDC, synthesis validation, and front-end signoff for production silicon- Collaborated with DFT, Physical Design, and Validation teams to ensure first-silicon success- Contributed to multi-node (Intel + TSMC) SoC integration, improving portability and reuse

Education

• AMIETE

  Bachelor’s Degree, Electronics and Telecommunication Engineering

  2013 — 2015

• Birla Institute of Technology and Science, Pilani

  Master's degree, VLSI

  2017 — 2018

• Govt. Institute Of Electronics

  Embedded Systems

  2009 — 2011

• C.B.M High School

  High School, General Studies

  2003 — 2007

• Birla Institute of Technology and Science, Pilani

  Master of Technology, VLSI

• Sandeepani School Of VLSI

  Associate’s Degree, VLSI

  2012 — 2012

Skills

• Rtl Design
• Fpga
• Asic
• Vhdl
• Verilog
• C
• Functional Verification