Rajkumar Patidar

About Rajkumar Patidar

Experienced in IP & Subsystem Verification domain.Technical Skills –• Worked as DV lead for sub-system verification and delivered successful projects covering all phases from specification to verified RTL & netlist across different product lines, mobile, compute, automotive.• Experience on verilog HDL and system verilog HVL, Methodology – OVM, UVM.• Experience on development of verification test plan, verification components for IP & SS DV and achieving verification goals for milestone.• Handled & developed expertise on power aware verification for subsystems at RTL and GLS level.• Worked on SoC level verification for chip clock controller block.• Strong hands-on debugging on RTL for IP and subsystems.• Worked on compute subsystems, functional safety features, DisplayPort1.2a, DisplayPort subsystems, HDMI, SD2.0 andAMBA APB, AHB, AXI, AXI-Stream, I2C, Native Video protocol, Video Over AXI-Streaming.• Tools – VCS,Verdi, DVE, Scripts – Python Management Skills –• Technical Requirement management - Discuss with design to finalizing on verification requirements.• Project Management - Project planning & execution while working as DV lead and individual contributor.• Leading & Mentoring - Lead & mentor small team of 5-6 DV engineers for subsystem verification

Experience

1. Manager Silicon Design Engineering

   AMD

   Jul 2024 — Present · Bengaluru, IN

   IP Verification Manager

Education

• Acropolise Institute of Technology & Research, Indore, (M.P.)

  B.E., Electronics and Communication

  2005 — 2009

• S.V. M. Khandwa, (M.P.)

  10 + 2, Science

  2004 — 2005

• Manipal Institute of Technology

  MTech, Microelectronics

  2010 — 2012

Skills

• Functional Verification
• Cadence Virtuoso
• Integrated Circuit Design
• Uvm
• Displayport
• Universal Verification Methodology (Uvm)
• Ncsim
• Xilinx Ise
• C
• Vlsi
• Fpga
• Digital Video
• Asic
• Modelsim
• Amba Apb/Ahb
• Verilog
• Vhdl
• Microelectronics
• Very-Large-Scale Integration (Vlsi)
• Perl
• Analog
• Sd/Sdio
• Digital Design
• Systemverilog
• Open Verification Methodology