Rajkumar Palwai

About Rajkumar Palwai

Analog and Mixed Signal Designer with good design experience in PLL ring and LC based, MEMS based Oscillators, sigma delta ADC, Bandgap and High Speed DRAM Memory I/O design. Designed both Ring and LC based oscillators at various speeds with ultra low jitter specs. Has very good understanding in PLL phase noise performance and hands on experience in lab measurements.Involved in the design & testing of different analog blocks required for the High speed Memory I/O\'s like PLL\'s, Receiver sampler, Duty cycle correctors, serializers, Band Gap circuits.Specialties: Strong Analog fundamentals, Ring & LC PLL design, sigma delta ADC, and phase noise (jitter) analysis, High speed I/O design, Pipeline ADC design.

Experience

1. Director of Circuit Design

   SiTime

   Feb 2022 — Present · Santa Clara County, CA, US

Education

• Osmania University

  B.E, Electronics & Communication

  2001 — 2005

• Indian Institute of Science (IISc)

  ME, Microelectronics

  2005 — 2007

Skills

• Oscillators
• Mems
• Speed
• Asic
• Pll
• Analog
• Ring
• Electronics
• Cadence Virtuoso
• Ic
• Serdes
• Ring and Lc Pll
• Cmos
• Pipeline Adc
• Verilog-a
• Analog Circuit Design
• Io Design
• Mixed Signal
• Circuit Design
• Simulations
• Vlsi
• Vco
• Integrated Circuit Design
• High Speed Io Design