Rajiv Srivastava

About Rajiv Srivastava

ASIC Architecture, Logic design - RTL IP (Verilog & SystemC/TLM)- Low power…

Experience

1. Senior Technologist

   Sandisk

   Feb 2025 — Present

Education

• Indian Institute of Technology (Banaras Hindu University), Varanasi

  M Tech, Micro-electronics

  1997 — 1999

• Madan Mohan Malaviya University of Technology

  B.E., Electronics

  1993 — 1997

Skills

• Rtl Design
• Functional Verification
• Systemc
• Formal Verification
• Digital Signal Processors
• Vlsi
• Ic
• Verilog
• Axi
• Logic Design
• Debugging
• Static Timing Analysis
• Xilinx
• Systemverilog
• Usb
• Soc
• Low-Power Design
• Arm
• Fpga
• Asic
• Semiconductors
• H.264
• Hardware Architecture
• Vhdl
• Ocp
• Amba Ahb
• Emulation
• High Level Synthesis
• Computer Architecture
• Rtl Coding
• Logic Synthesis
• Timing Closure
• Modelsim