Rajiv Pandey
Staff Engineer, Asic Design @SiriusXM
Deerfield Beach, FL, US
EMAILS
r••••••••@siriusxm.com
MOBILE NUMBERS
+12•••••••72
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WORK HISTORY
May 2017 — Present
Staff Engineer, Asic Design @SiriusXM
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Deerfield Beach, FL, US
EDUCATION
N/A
University Of Pune, Pune
Bachelor of Engineering, Electronics & Telecommunication
2009 — 2010
University of Southern California
Masters, Electrical Engineering
SKILLS
CmosIntegrated Circuits (Ic)Very-Large-Scale Integration (Vlsi)VlsiSystemverilogStatic Timing AnalysisNcsimCadence VirtuosoPhysical DesignPerlLogic DesignSystem on a Chip (Soc)FpgaAsicVerilogLabviewField-Programmable Gate Arrays (Fpga)Rtl DesignSocModelsimXilinx IseIcLtspiceApplication-Specific Integrated Circuits (Asic)
ABOUT RAJIV PANDEY
Senior Engineer at Qualcomm Proficient in RTL design, Logic Synthesis, Static timing analysis and Logic equivalence checking.
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