Rajesh Yadav

About Rajesh Yadav

Rajesh has 7+ years of experience in Physical Design including RTL Synthesis, Low power Implementation, and STA. He works with Samsung Semiconductor India Research (SSIR), Bangalore in the SOC-Design team as a PI/PD Engineer. Rajesh is experienced in RTL Synthesis and optimization, Physical design including critical blocks STA closure, Physical signoff, EM, and IR closure, of many complex and challenging blocks in lower technology nodes like 4nm, and 7nm. Rajesh has also experience in Low power design, SDC cleanup, and sanity clean up like LEC, LPRC (VSLP), LDRC (Spyglass).He has worked on leading EDA tools like Fusion Compiler, Design Compiler, Genus, Innovus, ICC2, Calibre, ICV, RedHawk, primeTime, Tempus, Formality, VSLP, Spyglass and many more. He has a keen interest in scripting to make his work easy and smarter using tcl, csh, bash Perl and Python scripting languages.Before joining the SSIR, Rajesh worked with eInfochips Ahmedabad and IIT Gandhinagar. Rajesh has done M.Tech in VLSI Design from the NorthCap University Gurugram and B.Tech in Electronics and Communication Engineering from Ranchi University, Ranchi.

Experience

1. Staff Engineer

   Samsung Semiconductor

   Mar 2024 — Present · Bengaluru, IN

Education

• Indian Institute of Technology Gandhinagar

  Course Audit, Electrical Engineering

  2016 — 2018

• Ranchi University

  Bachelor of Technology (B.Tech.), Electronics and Communication Engineering

  2004 — 2008

• The NorthCap University

  Master’s Degree, VLSI DESIGN

  2013 — 2015

Skills

• Public Speaking
• C++
• Payton
• Cadence
• Algorithms
• Physical Design
• Orcad Capture Cis
• Cadence Virtuoso
• Simulink
• Data Structures
• Rtl Compiler
• Xilinx
• Questasim
• Lt Spice
• C
• Matlab
• Embeded C
• Open Office
• Microsoft Office
• Vlsi
• Modelsim
• Tanner Eda
• Unix Shell Scripting
• Python
• Kiel Microvision
• Embedded C
• Virtual Lab
• Research
• Unix Operating Systems
• 8051 Microcontroller
• Encounter® Rtl Compiler
• Verilog
• Ni Labview
• System Verilog
• Project Management
• Labview
• Red Hat Linux
• Windows
• Logic Synthesis
• Fpga Prototyping