Rajesh Rama Chandran

About Rajesh Rama Chandran

Digital Design Architect with 20+ years of experience in Analog Devices, Intel and Qualcomm.Experienced in Cache Coherent NoCs, HDMI & Video Decoders, Time-of-Flight, FPGA Smart-NICs.Design ownership of Cache Coherent Nocs for Qualcomm Snapdragon SoCs. Involved in design, support to performance analysis, pre and post silicon debug support, Synthesis and timing closure and PPA comparison. Handled technical leadership roles as Chip-Lead and Digital Design Lead. Headed the Chip development for a breakthrough complex mixed signal ASIC on a new process node and achieved first silicon success. Delivered Digital Subsystems for multiple tape-outs (15+) of Video ASICs from Architecture till Signoff; with direct involvement and leadership to ensure quality and PPA metrics. Key strengths on Systems/Digital Architecture and Design. Owned and delivered on DigitalVerification at IP and chip level; DFT for Automotive ASICs; and supported multiple products for Siliconbring up, ATE program bring up and Silicon Debug. Hands on experience with FPGA emulation; including delivery of a custom FPGA IP to lead customer.

Experience

1. Senior Staff Engineer

   Qualcomm

   May 2023 — Present · Bengaluru, IN

   Design ownership and delivery of Cache Coherent Nocs for Snapdragon SoCs. Responsible for a) competitive PPA designb) support for verification closure, c) support for synthesis and timing closure, d) silicon debug

Education

• Chinmaya Vidyalaya

  AISSCE (Class XII), Science Stream

• Seventh Day Adventist Higher Secondary School

  Class 10, ICSE

• National Institute of Technology Calicut

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

Skills

• Formal Verification
• Dft
• Spi
• Tetramax
• System on a Chip (Soc)
• Functional Verification
• Soc
• Verilog
• Nc-Verilog
• Field-Programmable Gate Arrays (Fpga)
• Fpga
• Asic
• Perl
• Synopsys Primetime
• Matlab
• Vlsi
• Application-Specific Integrated Circuits (Asic)
• Rtl Design
• Digital Design
• Integrated Circuit Design
• Python
• Very-Large-Scale Integration (Vlsi)
• I2c
• Rtl Coding
• Systemverilog
• Atpg
• Ncsim
• Object-Oriented Programming (Oop)
• Primetime
• Logic Synthesis
• Static Timing Analysis
• Synopsys Tools
• Hdmi
• Tcl
• Analog
• C
• Timing Closure