Yerra Rajesh

About Yerra Rajesh

I started working as SOC Design Engineer at Intel in the PCIe domain (Knowledge: RTL Design, integration and Quality checks in PCIE subsystem) 2. Experience in Protocol Bridges RTL Design (Protocol Knowledge: CXL, PCIE, UCIe, AMBA etc.)3. Knowlege on LINT, Power Artist, FEV, Caliber, CDC, VCLP, Defacto, Collage, Quartus Prime, FC, DFT.4. Experienced in front-end digital design and verification of an IP/SoC besides SoC integration, validation, and post-silicon bring-up. Involved in all aspects of several IPs integration and features definition to RTL coding, verification, synthesis.5. Recognitions received at the Team level and Business Unit level for the contributions towards RTL Insertion and Debug.6. MTech focused on Communication Engineering from IIT Guwahati. B.Tech in Electronics & Communication at Nuzvid.

Experience

1. Soc Design Engineer

   Intel

   Jul 2020 — Present · Bengaluru, IN

   I started working as SOC Design Engineer at Intel in the PCIe domain.– Worked on Front-End RTL Design/Integration on interfaces like PCIe, CXL, and UCIe, with three years focused on the PCIe subsystem for discrete graphics SOCs.– Worked on Protocol Bridges(iCXL2UFI) RTL design, Integration, and architecture.– Knowledge of AMBA protocols (APB, AHB, AXI, CHI). I worked on a couple of projects where these AMBA protocols were used.– Strong knowledge of Different Industry Tools -Power Artist, Spyglass Lint, VCS, CDC, LEC, Verdi, VCLP, Defacto, Collage, Quartus Prime, FC, SGDFT– Functional debugging, worked with the Verification team to define review test plans and coverage analysis.– I worked for different SoCs, from 0P0 to Power On.– Proposed and implemented extra release checks at the subsystem level and added additional automation scripts to the gatekeeper to increase the Quality of the Release.– Responsible for debugging and fixing the issues at IP and SoC levels and working with Verification Team to improve the coverage of IPs.– Skills: RTL Coding · RTL Lint · UPF · VCLP Subsystem/SOC Integration · CDC · Synthesis · Defacto · SDC Constraints · Caliber · RTL quality checks· PCIe registers· Security and RAS· System Verilog· Milestone checklist· Perl· Python· Firmware· RDL, DFT, Timing

Education

• RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID

  PUC, MBiPC

  2011 — 2013

• Indian Institute of Technology, Guwahati

  Master's degree, Electrical, Electronics and Communications Engineering

  2018 — 2020

• RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID

  Bachelor of Technology - BTech, Electronics and Communications Engineering

  2013 — 2017