Rajesh Yadav

About Rajesh Yadav

To put in all my skill and knowledge acquired over time in constructive, innovative, result oriented projects and hence utilize my technical knowledge to accomplish the work thereby helping in the overall growth of the organization.I am Physical Design & Implementation Engineer involved with design of Block & SOC from Netlist to GDS on 5nm, 7nm, 8nm, 16nm and 28nm technology-• 5+ years of experience in Physical Design flow. • Have Good understanding of ASIC physical design from RTL to GDS-II using Synopsys and Cadence tool suite. • Experience in full chip Low Power Signoff along with upf debug. • Experience in timing closure and sdc validation along with formal verification of digital design with more than 2M instances. • Good understanding of reliability issues like IR drop, EM, ESD and antenna effects. • Experience in physical verification including LVS and ERC. • Clock tree setup/debug and synthesis for optimal QoR-Skill - Low Power, STA,Floor planning, PnR, CTS, Physical verification Tools- ICC2, Prime Time, DC, Innovus, Calibre, Encounter, VC static, Formality.

Experience

1. Engineering Manager

   NVIDIA

   Jun 2025 — Present

Education

• Maharashtra Institute of Technology

  Bachelor of Technology - BTech, Electrical, Electronic and Communications Engineering

  2009 — 2013

• Kendriya Vidyalaya

  AISSCE

  2007 — 2008

• Kendriya vidyalaya udhampur

  AISSE

  2005 — 2006

• Indian Institute of Technology, Kanpur

  Master of Technology - MTech, Electrical, Electronics and Communications Engineering

  2013 — 2015